Datasheet

595
AT32UC3A
30.8.2.20 USB Device DMA Channel X Status Register (UDDMAX_STATUS)
Offset: 0x031C + (X - 1) . 0x10
Register Name: UDDMAX_STATUS, X in [1..6]
Access Type: Read/Write
Reset Value: 0x00000000
• CH_EN: Channel Enabled
If set, the DMA channel is currently enabled.
If cleared, the DMA channel does no longer transfer data.
• CH_ACTIVE: Channel Active
If set, the DMA channel is currently trying to source USB data.
If cleared, the DMA channel is no longer trying to source USB data.
When a USB data transfer is completed, this bit is automatically reset.
• EOT_STA: End of USB Transfer Status
Set by hardware when the completion of the usb data transfer has closed the dma transfer. It is valid only if
BUFF_CLOSE_EN=1.
This bit is automatically cleared when read by software.
• EOCH_BUFF_STA: End of Channel Buffer Status
Set by hardware when the Channel Byte Count downcounts to zero.
This bit is automatically cleared when read by software.
• DESC_LD_STA: Descriptor Loaded Status
Set by hardware when a Descriptor has been loaded from the HSB bus.
This bit is automatically cleared when read by software.
31 30 29 28 27 26 25 24
CH_BYTE_CNT
ru
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
CH_BYTE_CNT
ru
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
–
DESC_LD_
STA
EOCH_BUFF_
STA
EOT_STA – – CH_ACTIVE CH_EN
ru ru ru rwu rwu
0 0 0 0 0
32058K
AVR32-01/12