Datasheet

585
AT32UC3A
30.8.2.15 USB Endpoint X Control Clear Register (UECONXCLR)
Offset: 0x0220 + X . 0x04
Register Name: UECONXCLR, X in [0..6]
Access Type: Write-Only
Read Value: 0x00000000
• TXINEC: Transmitted IN Data Interrupt Enable Clear
Set to clear TXINE.
Clearing has no effect.
Always read as 0.
• RXOUTEC: Received OUT Data Interrupt Enable Clear
Set to clear RXOUTE.
Clearing has no effect.
Always read as 0.
• RXSTPEC: Received SETUP Interrupt Enable Clear
Set to clear RXSTPE.
Clearing has no effect.
Always read as 0.
• UNDERFEC: Underflow Interrupt Enable Clear
Set to clear UNDERFE.
Clearing has no effect.
Always read as 0.
• NAKOUTEC: NAKed OUT Interrupt Enable Clear
Set to clear NAKOUTE.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – STALLRQC – – EPDISHDMAC
w w
0 0
15 14 13 12 11 10 9 8
– FIFOCONC – NBUSYBKEC – – – –
w w
0 0
7 6 5 4 3 2 1 0
SHORT
PACKETEC
STALLEDEC/
CRCERREC
OVERFEC NAKINEC NAKOUTEC
RXSTPEC/
UNDERFEC
RXOUTEC TXINEC
w w w w w w w w
0 0 0 0 0 0 0 0
32058K
AVR32-01/12