Datasheet

558
AT32UC3A
Note that this interrupt is generated even if the clock is frozen by the FRZCLK bit.
• EORSM: End of Resume Interrupt Flag
Set by hardware when the USB controller detects a valid “End of Resume” signal initiated by the host. This triggers a USB
interrupt if EORSME = 1.
Shall be cleared by software (by setting the EORSMC bit) to acknowledge the interrupt.
• UPRSM: Upstream Resume Interrupt Flag
Set by hardware when the USB controller sends a resume signal called “Upstream Resume”. This triggers a USB interrupt
if UPRSME = 1.
Shall be cleared by software (by setting the UPRSMC bit) to acknowledge the interrupt (USB clock inputs must be enabled
before).
• EPXINT, X in [0..6]: Endpoint X Interrupt Flag
Set by hardware when an interrupt is triggered by the endpoint X (UESTAX, UECONX). This triggers a USB interrupt if
EPXINTE = 1.
Cleared by hardware when the interrupt source is serviced.
• DMAXINT, X in [1..6]: DMA Channel X Interrupt Flag
Set by hardware when an interrupt is triggered by the DMA channel X. This triggers a USB interrupt if DMAXINTE = 1.
Cleared by hardware when the UDDMAX_STATUS interrupt source is cleared.
32058K
AVR32-01/12