Datasheet

497
AT32UC3A
30. USB On-The-Go Interface (USBB)
Rev: 3.1.1.1
30.1 Features
• USB 2.0 Compliant, Full-/Low-Speed (FS/LS) and On-The-Go (OTG), 12 Mbit/s
• 7 Pipes/Endpoints
• 960 bytes of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints
• Up to 2 Memory Banks per Pipe/Endpoint (Not for Control Pipe/Endpoint)
• Flexible Pipe/Endpoint Configuration and Management with Dedicated DMA Channels
• On-Chip Transceivers Including Pull-Ups/Pull-downs.
• On-Chip OTG pad including VBUS analog comparator
30.2 Description
The Universal Serial Bus (USB) MCU device complies with the Universal Serial Bus (USB) 2.0
specification, but it does NOT feature high-speed USB (480 Mbit/s).
Each pipe/endpoint can be configured in one of several transfer types. It can be associated with
one or more banks of a dual-port RAM used to store the current data payload. If several banks
are used (“ping-pong” mode), then one DPRAM bank is read or written by the CPU or the DMA
while the other is read or written by the USB macro core. This feature is mandatory for isochro-
nous pipes/endpoints.
Table 30-1 describes the hardware configuration of the USB MCU device.
The theoretical maximal pipe/endpoint configuration (1600 bytes) exceeds the real DPRAM size
(960 bytes). The user needs to be aware of this when configuring pipes/endpoints. To fully use
the 960 bytes of DPRAM, the user could for example use the configuration described in Table
30-2.
Table 30-1. Description of USB Pipes/Endpoints
Pipe/Endpoint Mnemonic Max. Size Max. Nb. Banks DMA Type
0 PEP0 64 bytes 1 N Control
1 PEP1 bytes Y Isochronous/Bulk/Interrupt
2 PEP2 bytes Y Isochronous/Bulk/Interrupt
3 PEP3 64 bytes Y Bulk/Interrupt
4 PEP4 64 bytes Y Bulk/Interrupt
5 PEP5 bytes Y Isochronous/Bulk/Interrupt
6 PEP6 bytes Y Isochronous/Bulk/Interrupt
Table 30-2. Example of Configuration of Pipes/Endpoints Using the Whole DPRAM
Pipe/Endpoint Mnemonic Size Nb. Banks
0 PEP0 64 bytes 1
1 PEP1 64 bytes 2
2 PEP2 64 bytes 2
3 PEP3 64 bytes 1
32058K
AVR32-01/12