Datasheet

455
AT32UC3A
0x8C Transmitted Pause Frames Register TPF Read/Write 0x0000_0000
0x90 Hash Register Bottom [31:0] Register HRB Read/Write 0x0000_0000
0x94 Hash Register Top [63:32] Register HRT Read/Write 0x0000_0000
0x98 Specific Address 1 Bottom Register SA1B Read/Write 0x0000_0000
0x9C Specific Address 1 Top Register SA1T Read/Write 0x0000_0000
0xA0 Specific Address 2 Bottom Register SA2B Read/Write 0x0000_0000
0xA4 Specific Address 2 Top Register SA2T Read/Write 0x0000_0000
0xA8 Specific Address 3 Bottom Register SA3B Read/Write 0x0000_0000
0xAC Specific Address 3 Top Register SA3T Read/Write 0x0000_0000
0xB0 Specific Address 4 Bottom Register SA4B Read/Write 0x0000_0000
0xB4 Specific Address 4 Top Register SA4T Read/Write 0x0000_0000
0xB8 Type ID Checking Register TID Read/Write 0x0000_0000
0xBC Transmit Pause Quantum Register TPQ Read/Write 0x0000_FFFF
0xC0 User Input/output Register USRIO Read/Write 0x0000_0000
0xC4 Wake on LAN Register WOL Read/Write 0x0000_0000
0xC8 - 0xFC Reserved – – –
Table 29-6. Ethernet MAC (MACB) Register Mapping (Continued)
Offset Register Name Access Reset Value
32058K
AVR32-01/12