Datasheet

425
AT32UC3A
28.8.1 SDRAMC Mode Register
Register Name: MR
Access Type: Read/Write
Reset Value: 0x00000000
•
MODE: SDRAMC Command Mode
This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – – –
MODE
Table 28-9.
MODE Description
0 0 0 Normal mode. Any access to the SDRAM is decoded normally.
0 0 1 The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle.
0 1 0
The SDRAM Controller issues an “All Banks Precharge” command when the SDRAM device is accessed
regardless of the cycle.
0 1 1
The SDRAM Controller issues a “Load Mode Register” command when the SDRAM device is accessed
regardless of the cycle. The command will load the CAS latency from the Configuration Register and every other
value set to 0 into the Mode Register.
1 0 0
The SDRAM Controller issues an “Auto-Refresh” Command when the SDRAM device is accessed regardless of
the cycle. Previously, an “All Banks Precharge” command must be issued.
1 0 1
The SDRAM Controller issues an extended load mode register command when the SDRAM device is accessed
regardless of the cycle. The command will load the PASR, DS and TCR from the Low Power Register and every
other value set to 0 into the Extended Mode Register.
1 1 0 Deep power-down mode. Enters deep power-down mode.
32058K
AVR32-01/12