Datasheet

395
AT32UC3A
27.6.7.3 Ready Mode
In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins
the access by down counting the setup and pulse counters of the read/write controlling signal. In
the last cycle of the pulse phase, the resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in Figure 27-29 and Figure 27-30. After
deassertion, the access is completed: the hold step of the access is performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to
indicate its ability to complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the
pulse of the controlling read/write signal, it has no impact on the access length as shown in Fig-
ure 27-30.
Figure 27-29. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11).
CLK_SMC
A[25:2]
NBS0, NBS1,
A0, A1
NW E
NCS
D[15:0]
6 5 4
4
3
3
2
2 1 0
1
0
1 1
0
FROZEN STATE
NW AIT
Internally synchronized
NW AIT signal
W rite cycle
EXNW _M O DE = 11 (Ready m ode)
W RITE_M O DE = 1 (NW E_controlled)
NW E_PULSE = 5
NCS_W R_PULSE = 7
0
32058K
AVR32-01/12