Datasheet

379
AT32UC3A
Figure 27-13. Write Cycle
–Write Cycle
The write_cycle time is defined as the total duration of the write cycle, that is, from the time
where address is set on the address bus to the point where address may change. The total write
cycle time is equal to:
NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD
= NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD
All NWE and NCS (write) timings are defined separately for each chip select as an integer num-
ber of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user
must define the total write cycle instead of the hold timing. This implicitly defines the NWE hold
time and NCS (write) hold times as:
NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE
– Null Delay Setup and Hold
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active
continuously in case of consecutive write cycles in the same memory (see Figure 27-14). How-
ever, for devices that perform write operations on the rising edge of NWE or NCS, such as
SRAM, either a setup or a hold must be programmed.
CLK_SMC
A[25:2]
NBS0, NBS1,
A0, A1
NWE
NCS
NWE_SETUP
NWE_PULSE
NCS_WR_SETUP
NCS_WR_PULSE
NWE_CYCLE
NWE_HOLD
NCS_WR_HOLD
32058K
AVR32-01/12