Datasheet

374
AT32UC3A
27.6.4.1 Read Waveforms
The read cycle is shown on Figure 27-9.
The read cycle starts with the address setting on the memory address bus, i.e.:
{A[25:2], A1, A0} for 8-bit devices
{A[25:2], A1} for 16-bit devices
A[25:2] for 32-bit devices.
Figure 27-9. Standard Read Cycle
– NRD Waveform
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD
falling edge;
2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD ris-
ing edge;
3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD ris-
ing edge.
A[25:2]
CLK_SMC
NBS0, NBS1,
A0, A1
NRD
NCS
D[15:0]
NCS_RD_SETUP
NRD_SETUP NRD_PULSE
NCS_RD_PULSE
NRD_CYCLE
NRD_HOLD
NCS_RD_HOLD
32058K
AVR32-01/12