Datasheet
344
AT32UC3A
1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors gener-
ate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag
ITERATION is asserted.
• INACK: Inhibit Non Acknowledge
0: The NACK is generated.
1: The NACK is not generated.
• OVER: Oversampling Mode
0: 16x Oversampling.
1: 8x Oversampling.
• CLKO: Clock Output Select
0: The USART does not drive the CLK pin.
1: The USART drives the CLK pin if USCLKS does not select the external clock CLK.
• MODE9: 9-bit Character Length
0: CHRL defines character length.
1: 9-bit character length.
• MSBF/CPOL: Bit Order or SPI Clock Polarity
– If USART does not operate in SPI Mode (MODE … 0xE and 0xF):
MSBF = 0: Least Significant Bit is sent/received first.
MSBF = 1: Most Significant Bit is sent/received first.
– If USART operates in SPI Mode (Slave or Master, MODE = 0xE or 0xF):
CPOL = 0: The inactive state value of SPCK is logic level zero.
CPOL = 1: The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required
clock/data relationship between master and slave devices.
• CHMODE: Channel Mode
• NBSTOP: Number of Stop Bits
CHMODE Mode Description
0 0 Normal Mode
0 1 Automatic Echo. Receiver input is connected to the TXD pin.
1 0 Local Loopback. Transmitter output is connected to the Receiver Input..
1 1 Remote Loopback. RXD pin is internally connected to the TXD pin.
NBSTOP Asynchronous (SYNC = 0) Synchronous (SYNC = 1)
0 0 1 stop bit 1 stop bit
32058K
AVR32-01/12