Datasheet

298
AT32UC3A
25.9.16 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x4C
Reset value: 0x00000000
• RXSYN: Rx Sync Interrupt Mask
0: The Rx Sync Interrupt is disabled.
1: The Rx Sync Interrupt is enabled.
• TXSYN: Tx Sync Interrupt Mask
0: The Tx Sync Interrupt is disabled.
1: The Tx Sync Interrupt is enabled.
• CP1: Compare 1 Interrupt Mask
0: The Compare 1 Interrupt is disabled.
1: The Compare 1 Interrupt is enabled.
• CP0: Compare 0 Interrupt Mask
0: The Compare 0 Interrupt is disabled.
1: The Compare 0 Interrupt is enabled.
• RXBUFF: Receive Buffer Full Interrupt Mask
0: The Receive Buffer Full Interrupt is disabled.
1: The Receive Buffer Full Interrupt is enabled.
• ENDRX: End of Reception Interrupt Mask
0: The End of Reception Interrupt is disabled.
1: The End of Reception Interrupt is enabled.
• OVRUN: Receive Overrun Interrupt Mask
0: The Receive Overrun Interrupt is disabled.
1: The Receive Overrun Interrupt is enabled.
• RXRDY: Receive Ready Interrupt Mask
0: The Receive Ready Interrupt is disabled.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – RXSYN TXSYN CP1 CP0
7 6 5 4 3 2 1 0
RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY
32058K
AVR32-01/12