Datasheet

284
AT32UC3A
25.9.6 Transmit Frame Mode Register
Name: TFMR
Access Type: Read/Write
Offset: 0x1C
Reset value: 0x00000000
• FSLENHI: Transmit Frame Sync Length High part
The four MSB of the FSLEN bitfield.
• FSEDGE: Frame Sync Edge Detection
Determines which edge on frame sync will generate the interrupt TXSYN (Status Register).
• FSDEN: Frame Sync Data Enable
0: The TX_DATA line is driven with the default value during the Transmit Frame Sync signal.
1: TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
• FSOS: Transmit Frame Sync Output Selection
• FSLEN: Transmit Frame Sync Length
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync
Data Register if FSDEN is 1. Note: The four most significant bits fo this bitfield are in the FSLENHI bitfield.
31 30 29 28 27 26 25 24
FSLENHI – – – FSEDGE
23 22 21 20 19 18 17 16
FSDEN FSOS FSLEN
15 14 13 12 11 10 9 8
– – – – DATNB
7 6 5 4 3 2 1 0
MSBF – DATDEF DATLEN
FSEDGE Frame Sync Edge Detection
0x0 Positive Edge Detection
0x1 Negative Edge Detection
FSOS Selected Transmit Frame Sync Signal TX_FRAME_SYNC Pin
0x0 None Input-only
0x1 Negative Pulse Output
0x2 Positive Pulse Output
0x3 Driven Low during data transfer Output
0x4 Driven High during data transfer Output
0x5 Toggling at each start of data transfer Output
0x6-0x7 Reserved Undefined
32058K
AVR32-01/12