Datasheet

279
AT32UC3A
• CKG: Receive Clock Gating Selection
• CKI: Receive Clock Inversion
0: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal out-
put is shifted out on Receive Clock rising edge.
1: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal out-
put is shifted out on Receive Clock falling edge.
CKI affects only the Receive Clock and not the output clock signal.
• CKO: Receive Clock Output Mode Selection
• CKS: Receive Clock Selection
CKG Receive Clock Gating
0x0
None, continuous clock
0x1
Receive Clock enabled only if RX_FRAME_SYNC Low
0x2
Receive Clock enabled only if RX_FRAME_SYNC High
0x3
Reserved
CKO Receive Clock Output Mode RX_CLOCK pin
0x0 None Input-only
0x1 Continuous Receive Clock Output
0x2 Receive Clock only during data transfers Output
0x3-0x7 Reserved
CKS Selected Receive Clock
0x0
Divided Clock
0x1
TX_CLOCK Clock signal
0x2
RX_CLOCK pin
0x3
Reserved
32058K
AVR32-01/12