Datasheet

261
AT32UC3A
25.5 I/O Lines Description
25.6 Product Dependencies
25.6.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC
receiver I/O lines to the SSC peripheral mode.
Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC
transmitter I/O lines to the SSC peripheral mode.
25.6.2 Power Management
The SSC clock is generated by the power manager. Before using the SSC, the programmer
must ensure that the SSC clock is enabled in the power manager.
In the SSC description, Master Clock (CLK_SSC) is the bus clock of the peripheral bus to which
the SSC is connected.
25.6.3 Interrupt
The SSC interface has an interrupt line connected to the interrupt controller. Handling interrupts
requires programming the interrupt controller before configuring the SSC.
All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each
pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt ser-
vice routine can get the interrupt origin by reading the SSC interrupt status register.
25.7 Functional Description
This chapter contains the functional description of the following: SSC Functional Block, Clock
Management, Data format, Start, Transmitter, Receiver and Frame Sync.
The receiver and transmitter operate separately. However, they can work synchronously by pro-
gramming the receiver to use the transmit clock and/or to start a data transfer when transmission
starts. Alternatively, this can be done by programming the transmitter to use the receive clock
and/or to start a data transfer when reception starts. The transmitter and the receiver can be pro-
grammed to operate with the clock signals provided on either the TX_CLOCK or RX_CLOCK
pins. This allows the SSC to support many slave-mode data transfers. The maximum clock
speed allowed on the TX_CLOCK and RX_CLOCK pins is the master clock divided by 2.
Table 25-1. I/O Lines Description
Pin Name Pin Description Type
RX_FRAME_SYNC Receiver Frame Synchro Input/Output
RX_CLOCK Receiver Clock Input/Output
RX_DATA Receiver Data Input
TX_FRAME_SYNC Transmitter Frame Synchro Input/Output
TX_CLOCK Transmitter Clock Input/Output
TX_DATA Transmitter Data Output
32058K
AVR32-01/12