Datasheet

246
AT32UC3A
24.14 Two-wire Interface (TWI) User Interface
24.14.1 Register Mapping
Note: 1. Values in the Version Register vary with the version of the IP block implementation.
24.14.2 TWI Control Register
Name: CR
Access: Write-only
Reset Value: 0x00000000
• START: Send a START Condition
0 = No effect.
1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
Table 24-4. TWI User Interface
Offset Register Name Access Reset
0x00 Control Register CR Write-only N / A
0x04 Master Mode Register MMR Read-write 0x00000000
0x08 Slave Mode Register SMR Read-write 0x00000000
0x0C Internal Address Register IADR Read-write 0x00000000
0x10 Clock Waveform Generator Register CWGR Read-write 0x00000000
0x20 Status Register SR Read-only 0x0000F009
0x24 Interrupt Enable Register IER Write-only N / A
0x28 Interrupt Disable Register IDR Write-only N / A
0x2C Interrupt Mask Register IMR Read-only 0x00000000
0x30 Receive Holding Register RHR Read-only 0x00000000
0x34 Transmit Holding Register THR Write-only 0x00000000
0x38 - 0xF8 Reserved – – –
0xFC Version Register TWI_VER Read-only 0x00000000
(1)
0x38 - 0xFC Reserved – – –
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
SWRST – SVDIS SVEN MSDIS MSEN STOP START
32058K
AVR32-01/12