Datasheet

239

AT32UC3A

As soon as data is written in the THR, TXRDY (Transmit Holding Register Ready) flag is reset,

and it is set when the shift register is empty and the sent data acknowledged or not. If the data is

not acknowledged, the NACK flag is set.

Note that a STOP or a repeated START always follows a NACK.

See Figure 24-23 on page 240.

24.13.4.2 Write Sequence

In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register

Ready) flag is set as soon as a character has been received in the RHR (TWI Receive Holding

TWI continues receiving data until a STOP condition or a REPEATED_START + an address dif-

ferent from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set

and SVACC reset.

See Figure 24-24 on page 241.

24.13.4.3 Clock Synchronization Sequence

In the case where THR or RHR is not written/read in time, TWI performs a clock synchronization.

Clock stretching information is given by the SCLWS (Clock Wait state) bit.

See Figure 24-26 on page 242 and Figure 24-27 on page 243.

24.13.4.4 General Call

In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set.

After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL

and to decode the new address programming sequence.

See Figure 24-25 on page 241.

24.13.4.5 PDC

As it is impossible to know the exact number of data to receive/send, the use of PDC is NOT rec-

ommended in SLAVE mode.

32058K

AVR32-01/12