Datasheet

219
AT32UC3A
Otherwise, the following equations determine the delay:
If FDIV is 0:
If FDIV is 1:
Note: N = 32
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
If FDIV is 0:
If FDIV is 1:
N = 32
Delay Before SPCK
DLYBS
MCK
--------------------=
Delay Before SPCK
N DLYBS
×
MCK
------------------------------=
Delay Between Consecutive Transfers
32 DLYBCT×
------------------------------------
SCBR
MCK 2MCK
---------------- --+=
Delay Between Consecutive Transfers
32 N
× DLYBCT×
MCK
------------------------------------------------
N SCBR
×
2MCK
-------------------------+=
32058K
AVR32-01/12