Datasheet
187
AT32UC3A
22.5.13 Glitch Filter Enable Register
Name: GFER
Access: Read, Write, Set, Clear, Toggle
• P0-31: Glitch Filter Enable
0 = Glitch filter is disabled for the corresponding pin.
1 = Glitch filter is enabled for the corresponding pin.
NOTE! The value of this register should only be changed when IER is ‘0’. Updating this GFER while interrupt on the corre-
sponding pin is enabled can cause an unintentional interrupt to be triggered.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
32058K
AVR32-01/12