Datasheet

174
AT32UC3A
Figure 22-3. Interrupt timing with glitch filter disabled
The figure below shows the timing for rising edge (or pin-change) interrupts when the glitch filter
is enabled. For the pulse to be registered, it must be sampled on two subsequent rising edges.
In the example, the first pulse is rejected while the second pulse is accepted and causes an
interrupt request.
Figure 22-4. Interrupt timing with glitch filter enabled
clock
Pin Level
GPIO_IFR
clock
Pin Level
GPIO_IFR
32058K
AVR32-01/12