Datasheet

117
AT32UC3A
The flash controller supports flash blocks with up to 2^21 word addresses, as displayed in Fig-
ure 18-1. Reading the memory space between address pw and 2^21-1 returns an undefined
result. The User page is permanently mapped to word address 2^21.
Figure 18-1. Memory map for the Flash memories
18.4.5 Quick Page Read
A dedicated command, Quick Page Read (QPR), is provided to read all words in an
addressed page. All bits in all words in this page are AND’ed together, returning a 1-bit result.
This result is placed in the Quick Page Read Result (QPRR) bit in Flash Status Register
(FSR). The QPR command is useful to check that a page is in an erased state. The QPR
instruction is much faster than performing the erased-page check using a regular software
subroutine.
18.4.6 Write page buffer operations
The internal memory area reserved for the embedded flash can also be written through a
write-only page buffer. The page buffer is addressed only by the address bits required to
address w words (since the page buffer is word addressable) and thus wrap around within the
internal memory area address space and appear to be repeated within it.
When writing to the page buffer, the PAGEN field in the FCMD register is updated with the
page number corresponding to page address of the latest word written into the page buffer.
Table 18-1. User row addresses
Memory type Start address, byte sized Size
Main array 0 pw words = 4pw bytes
User 2^23 = 8388608 128 words = 512 bytes
0
pw -1
pw
2^21+128
UnusedFlash data array
U nused
U ser page
F lash w ith
extra page
2^21
A ll addresses are w ord addresses
32058K
AVR32-01/12