Datasheet
9Atmel ATA6826C [DATASHEET]
9213D–AUTO–09/12
3 Thermal Prewarning and Shutdown
3.1 Thermal prewarning set T
jPW set
120 145 170 °C B
3.2
Thermal prewarning
reset
T
jPW reset
105 130 155 °C B
3.3
Thermal prewarning
hysteresis
ΔT
jPW
15 °C B
3.4 Thermal shutdown off T
j switch off
150 175 200 °C B
3.5 Thermal shutdown on T
j switch on
135 160 185 °C B
3.6
Thermal shutdown
hysteresis
ΔT
j switch off
15 K B
3.7
Ratio thermal shutdown
off/thermal prewarning
set
T
j switch off/
T
jPW set
1.05 1.2 B
3.8
Ratio thermal shutdown
on/thermal prewarning
reset
T
j switch on/
T
jPW reset
1.05 1.2 B
4 Output Specification (OUT1-OUT3)
4.1
On resistance
I
Out 1-3
= –0.9A
2, 12,
13
R
DSOn1-3
0.8 1.5 Ω A
4.2 I
Out 1-3
= +0.9A
2, 12,
13
R
DSOn1-3
0.8 1.5 Ω A
4.3
High-side output
leakage current
V
Out 1-3
= 0V
,
output stages off
2, 12,
13
I
Out1-3
–15 µA A
4.4
Low-side output
leakage current
V
Out 1-3
= V
VS,
output stages off
2, 12,
13
I
Out1-3
200 µA A
4.5
High-side switch
reverse diode forward
voltage
I
Out 1-3
= 1.5A
2, 12,
13
V
Out1-3
– V
VS
2 V A
4.6
Low-side switch
reverse diode forward
voltage
I
Out 1-3
= –1.5A
2, 12,
13
V
Out 1-3
–2 V A
4.7
High-side overcurrent
limitation and shutdown
threshold
7.5V < V
S
< 20V
20V ≤ V
S
< 40V
2, 12,
13
I
Out1-3
–1.7
–2.0
–1.3
–1.3
–1.0
–1.0
A
A
A
4.8
Low-side overcurrent
limitation and shutdown
threshold
7.5V < V
S
< 20V
20V ≤ V
S
< 40V
2, 12,
13
I
Out1-3
1
1
1.3
1.3
1.7
2.0
A
A
A
4.9
Overcurrent shutdown
delay time
t
dSd
10 40 µs A
4.10
High-side open-load
detection threshold
2, 12,
13
I
Out1-3
–50 –30 –10 mA A
4.11
Low-side open-load
detection threshold
2, 12,
13
I
Out1-3
10 30 50 mA A
8. Electrical Characteristics (Continued)
7.5V < V
VS
< 40V; 4.75V < V
VCC
< 5.25V; INH = High; –40°C < T
j
< 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of
final level. Device not in standby for t > 1ms