Datasheet

8Atmel ATA5021 [DATASHEET]
9145G–AUTO–09/12
4. State Diagram
The kernel of the watchdog is a finite state machine. Figure 4-1 shows the state diagram with all possible states and
transmissions. Many transmissions are controlled by an internal timer. The numbers for the time-outs are the same as on the
pulse diagrams.
Figure 4-1. State Diagram of the Finite State Machine
Short
Window
Enable
State
Short
Window
Disable
State
Long
Window
Enable
State
Long
Window
Disable
State
2. wedge is the detection of a signal edge on the wake-up pin after the deboucing time
3. trg_ok is valid for once cycle after the rising edge on trg_d
4. trg_err is valid if the low period of trg_d is too long
1. mode_d and trg_d are the debounced signals of the MODE and TRG pins
Notes:
Reset
Out
State
Mode
Switch
State
Reset
State
time-out t
0
mode_d = 0
mode_d = 1
mode_d = 1
mode_d = 0
mode_d = 0
trg_ok
trg_d = 0
OR wedge
trg_ok
trg_d = 0
time-out t
2
time-out t
3
OR trg_err
time-out t
5
OR trg_err
OR wedge
time-out t
4
time-out t
1
time-out t
6