Datasheet

5Atmel ATA5021 [DATASHEET]
9145G–AUTO–09/12
The clock frequency determines all time periods of the logical part as shown in Section 7. “Electrical Characteristics” on page 9
under the subheading “Timing”.
3.3 Supply Voltage Monitoring, Pin 5
During ramp-up of the supply voltage and in the case of supply-voltage drops, the integrated power-on reset (POR) circuitry
sets the internal logic to a defined basic status and generates a reset pulse at the reset output, pin 5. A hysteresis in the POR
threshold prevents the circuit from oscillating. During ramp-up of the supply voltage, the reset output stays active for a specified
period of time (t
0
) in order to bring the microcontroller into its defined reset status (see Figure 3-1 on page 5).
3.4 Switch-over Mode Time, Pin 3
The switch-over mode time enables the synchronous operation of microcontroller and watchdog. When the power-on reset time
has elapsed, the watchdog has to be switched to monitoring mode by the microcontroller by a “low” signal transmitted to the
mode pin (pin 3) within the time-out period, t
1
. If the low signal does not occur within t1 (see Figure 3-1 on page 5), the watchdog
generates a reset pulse, t
6
, and t
1
starts again. Microcontroller and watchdog are synchronized with the switch-over mode time,
t
1
, each time a reset pulse is generated.
Figure 3-1. Power-on Reset and Switch-over Mode
100.00 0.23 40.07 38.88 –3.0%
100.00 0.47 78.07 78.00 –0.1%
100.00 1.04 167.76 164.00 –2.2%
100.00 4.75 733.17 730.00 –0.4%
100.00 10.49 1542.84 1530.00 –0.8%
119.50 0.23 47.81 46.38 –3.0%
119.50 0.47 93.20 93.00 –0.2%
119.50 1.04 200.37 200.25 –0.1%
119.50 4.75 875.90 870.00 –0.7%%
119.50 10.49 1843.26 1835.00 –0.4%%
Table 3-1. Comparison Table Clock Period Calculation versus Measurement on Test Board (Continued)
R1 (kΩ) C1 (nF)
Period “T” (µs) by New
Formula
Period “T” (µs) by
Measurement
Deviation of New Formula
versus Measurement
V
DD
Reset out
Mode Pin 3
Pin 5
Pin 6
t
0
t
1
t
6