Datasheet

10Atmel ATA5021 [DATASHEET]
9145G–AUTO–09/12
2.5 Pull-up current
V
IN
= 0V
V
VDD
= 5V
2, 3 I
PU
–20 –5 µA A
Outputs
3.1
Maximum output
current
4, 5 I
OUT
–2 +2 mA C
3.2 Logical output “low” I
OUT
= 1mA 4, 5 V
OL
0.2 V A
3.3 Logical output “high” I
OUT
= –1mA 4 V
OH
V
VDD
0.2
V A
3.4 Leakage current V
OUT
= 5V 5 I
leak
2 µA A
Timing
4.1 Frequency deviation
(1)
R
1
= 66kΩ
C
1
= 470pF
V
VDD
= 4.5V to 5V
(2)
8 f
dev
5 % C
4.2
Debounce time
2,3 t
deb1
3 4 Cycle D
4.3 1 t
deb2
96 128 Cycle D
4.4
Maximum trigger pulse
length
3 t
trgmax
45 Cycle D
4.5 Power-up reset time t
0
201 Cycle D
4.6 Switch-over mode time t
1
1112 Cycle D
4.7 Disable time
Short watchdog
window
t
2
130 Cycle D
4.8 Enable time
Short watchdog
window
t
3
124 Cycle D
4.9 Disable time
Long watchdog
window
t
4
71970 Cycle D
4.10 Enable time
Long watchdog
window
t
5
30002 Cycle D
4.11 Reset-out time t
6
40 Cycle D
7. Electrical Characteristics (Continued)
V
VDD
= 5V, T
amb
= –40°C to +125°C, reference point is pin 7, unless otherwise specified.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. Frequency deviation also depends on the tolerances of the external components
2. Cycle = Period of clock frequency (see Section 3.2 on page 4)