Datasheet

879
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is
detected, a passive error frame is sent. Also, after a transmission, an error passive unit waits before initiating further
transmission.
A bus off unit is not allowed to have any influence on the bus.
For fault confinement, two errors counters (TEC and REC) are implemented. These counters are accessible via the
CAN_ECR register. The state of the CAN controller is automatically updated according to these counter values. If the
CAN controller enters Error Active state, then the ERRA bit is set in the CAN_SR register. The corresponding interrupt is
pending while the interrupt is not masked in the CAN_IMR register. If the CAN controller enters Error Passive Mode, then
the ERRP bit is set in the CAN_SR register and an interrupt remains pending while the ERRP bit is set in the CAN_IMR
register. If the CAN enters Bus Off Mode, then the BOFF bit is set in the CAN_SR register. As for ERRP and ERRA, an
interrupt is pending while the BOFF bit is set in the CAN_IMR register.
When one of the error counters values exceeds 96, an increased error rate is indicated to the controller through the
WARN bit in CAN_SR register, but the node remains error active. The corresponding interrupt is pending while the
interrupt is set in the CAN_IMR register.
Refer to the Bosch CAN specification v2.0 for details on fault confinement.
Error Interrupt Handler
ERRA, WARN, ERRP and BOFF (CAN_SR) store the key transitions of the CAN bus status as defined in Figure 41-7 on
page 878. The transitions depend on the TEC and REC (CAN_ECR) values as described in Section “Fault Confinement”
on page 878.
These flags are latched to keep from triggering a spurious interrupt in case these bits are used as the source of an
interrupt. Thus, these flags may not reflect the current status of the CAN bus.
The current CAN bus state can be determined by reading the TEC and REC fields of CAN_ECR.
41.7.4.3 Overload
The overload frame is provided to request a delay of the next data or remote frame by the receiver node (“Request
overload frame”) or to signal certain error conditions (“Reactive overload frame”) related to the intermission field
respectively.
Reactive overload frames are transmitted after detection of the following error conditions:
 Detection of a dominant bit during the first two bits of the intermission field
 Detection of a dominant bit in the last bit of EOF by a receiver, or detection of a dominant bit by a receiver or a
transmitter at the last bit of an error or overload frame delimiter
The CAN controller can generate a request overload frame automatically after each message sent to one of the CAN
controller mailboxes. This feature is enabled by setting the OVL bit in the CAN_MR register.
Reactive overload frames are automatically handled by the CAN controller even if the OVL bit in the CAN_MR register is
not set. An overload flag is generated in the same way as an error flag, but error counters do not increment.
41.7.5 Low-power Mode
In Low-power Mode, the CAN controller cannot send or receive messages. All mailboxes are inactive.
In Low-power Mode, the SLEEP signal in the CAN_SR register is set; otherwise, the WAKEUP signal in the CAN_SR
register is set. These two fields are exclusive except after a CAN controller reset (WAKEUP and SLEEP are stuck at 0
after a reset). After power-up reset, the Low-power Mode is disabled and the WAKEUP bit is set in the CAN_SR register
only after detection of 11 consecutive recessive bits on the bus.
41.7.5.1 Enabling Low-power Mode
A software application can enable Low-power Mode by setting the LPM bit in the CAN_MR global register. The CAN
controller enters Low-power Mode once all pending transmit messages are sent.
When the CAN controller enters Low-power Mode, the SLEEP signal in the CAN_SR register is set. Depending on the
corresponding mask in the CAN_IMR register, an interrupt is generated while SLEEP is set.