Datasheet

805
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
Master Node Configuration
The user can choose between two DMAC modes by the PDCM bit in the LIN Mode register (US_LINMR):
 PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the DMAC in the Transmit
Holding register US_THR (instead of the LIN Mode register US_LINMR). Because the DMAC transfer size is
limited to a byte, the transfer is split into two accesses. During the first access the bits, NACT, PARDIS, CHKDIS,
CHKTYP, DLM and FSDIS are written. During the second access the 8-bit DLC field is written.
 PDCM = 0: the LIN configuration is not stored in the WRITE buffer and it must be written by the user in the LIN
Mode register (US_LINMR).
The WRITE buffer also contains the Identifier and the DATA, if the USART sends the response (NACT = PUBLISH).
The READ buffer contains the DATA if the USART receives the response (NACT = SUBSCRIBE).
Figure 39-51. Master Node with DMAC (PDCM = 1)
Figure 39-52. Master Node with DMAC (PDCM = 0)
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NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
DLC
IDENTIFIER
DATA 0
DATA N
WRITE BUFFER
(Peripheral) DMA
Controller
(Peripheral) DMA
Controller
USART3
LIN CONTROLLER
APB bus
NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
DLC
IDENTIFIER
DATA 0
DATA N
WRITE BUFFER
RXRDY
TXRDY
TXRDY
USART3
LIN CONTROLLER
APB bus
READ BUFFER
NODE ACTION = PUBLISH NODE ACTION = SUBSCRIBE
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RXRDY
TXRDY
TXRDY
APB bus
USART3
LIN CONTROLLER
DATA 0
DATA N
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WRITE BUFFER
USART3
LIN CONTROLLER
READ BUFFER
NODE ACTION = PUBLISH NODE ACTION = SUBSCRIBE
APB bus
IDENTIFIER
DATA 0
DATA N
WRITE BUFFER
IDENTIFIER
(Peripheral) DMA
Controller
(Peripheral) DMA
Controller