Datasheet

596
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
9. Program the LLI_W(n).DMAC_CFGx register for Channel x with the following field’s values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–DST_REP is set to zero. Address are contiguous.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host
Controller.
10. Program LLI_W(n).DMAC_DSCRx with the address of LLI_B(n) descriptor. And set the DSCRx_IF to the
AHB Layer ID. This operation actually links the Word oriented descriptor on the second byte oriented
descriptor. When block_length[1:0] is equal to 0 (multiple of 4) LLI_W(n).DMAC_DSCRx points to 0, only
LLI_W(n) is relevant.
11. Program the channel registers in the Memory for the second descriptor. This descriptor will be byte oriented.
This descriptor is referred to as LLI_B(n), standing for LLI Byte oriented.
12. The LLI_B(n).DMAC_SADDRx field in memory must be set with the starting address of the HSMCI_FIFO
address.
13. The LLI_B(n).DMAC_DADDRx is not relevant if previous word aligned descriptor was enabled. If 1, 2 or 3
bytes are transferred, that address is user defined and not word aligned.
14. Program LLI_B(n).DMAC_CTRLAx with the following field’s values:
–DST_WIDTH is set to BYTE.
–SRC_WIDTH is set to BYTE.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer).
15. Program LLI_B(n).DMAC_CTRLBx with the following field’s values:
–DST_INCR is set to INCR.
–SRC_INCR is set to INCR.
–FC field is programmed with peripheral to memory flow control mode.
–Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next descriptor
location points to 0.
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is
able to prefetch data and write HSMCI simultaneously.
16. Program LLI_B(n).DMAC_CFGx memory location for Channel x with the following field’s values:
–FIFOCFG defines the watermark of the DMAC channel FIFO.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host
Controller
17. Program LLI_B(n).DMAC_DSCR with address of descriptor LLI_W(n+1). If LLI_B(n) is the last descriptor,
then program LLI_B(n).DMAC_DSCR with 0.
18. Program the DMAC_CTRLBx register for Channel x with 0, its content is updated with the LLI Fetch
operation.
19. Program DMAC_DSCRx with the address of LLI_W(0) if block_length is greater than 4 else with address of
LLI_B(0).
20. Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request.
4. Enable DMADONE interrupt in the HSMCI_IER register.
5. Poll CBTC[x] bit in the DMAC_EBCISR Register.
6. If a new list of buffers shall be transferred, repeat step 7. Check and handle HSMCI errors.
7. Poll FIFOEMPTY field in the HSMCI_SR.