Datasheet

533
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
1 = Set by hardware when the UDPHS controller is in SUSPEND state and is re-activated by a filtered non-idle signal from the
UDPHS line (not by an upstream resume). This triggers a UDPHS interrupt when the WAKE_UP bit is set in UDPHS_IEN regis-
ter. When receiving this interrupt, the user has to enable the device controller clock prior to operation.
Note: this interrupt is generated even if the device controller clock is disabled.
• ENDOFRSM: End Of Resume Interrupt
0 = Cleared by setting the ENDOFRSM bit in UDPHS_CLRINT.
1 = Set by hardware when the UDPHS controller detects a good end of resume signal initiated by the host. This triggers a UDPHS
interrupt when the ENDOFRSM bit is set in UDPHS_IEN.
• UPSTR_RES: Upstream Resume Interrupt
0 = Cleared by setting the UPSTR_RES bit in UDPHS_CLRINT.
1 = Set by hardware when the UDPHS controller is sending a resume signal called “upstream resume”. This triggers a UDPHS
interrupt when the UPSTR_RES bit is set in UDPHS_IEN.
• EPT_x: Endpoint x Interrupt
0 = Reset when the UDPHS_EPTSTAx interrupt source is cleared.
1 = Set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the
EPT_x bit in UDPHS_IEN.
• DMA_x: DMA Channel x Interrupt
0 = Reset when the UDPHS_DMASTATUSx interrupt source is cleared.
1 = Set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit
in UDPHS_IEN.