Datasheet

527
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
32.7 USB High Speed Device Port (UDPHS) User Interface
Notes: 1. The reset value for UDPHS_EPTCTL0 is 0x0000_0001.
2. The addresses for the UDPHS Endpoint registers shown here are for UDPHS Endpoint0. The structure of this group
of registers is repeated successively for each endpoint according to the consecution of endpoint registers located
between 0x120 and 0x1DC.
3. The DMA channel index refers to the corresponding EP number. When no DMA channel is assigned to one EP, the
associated registers are reserved. This is the case for EP0, so DMA Channel 0 registers are reserved.
Table 32-6. Register Mapping
Offset Register Name Access Reset
0x00 UDPHS Control Register UDPHS_CTRL Read-write 0x0000_0200
0x04 UDPHS Frame Number Register UDPHS_FNUM Read-only 0x0000_0000
0x08 - 0x0C Reserved – – –
0x10 UDPHS Interrupt Enable Register UDPHS_IEN Read-write 0x0000_0010
0x14 UDPHS Interrupt Status Register UDPHS_INTSTA Read-only 0x0000_0000
0x18 UDPHS Clear Interrupt Register UDPHS_CLRINT Write-only –
0x1C UDPHS Endpoints Reset Register UDPHS_EPTRST Write-only –
0x20 - 0xCC Reserved – – –
0xE0 UDPHS Test Register UDPHS_TST Read-write 0x0000_0000
0xE4 - 0xE8 Reserved – – –
0x100 + endpoint * 0x20 + 0x00 UDPHS Endpoint Configuration Register UDPHS_EPTCFG Read-write 0x0000_0000
0x100 + endpoint * 0x20 + 0x04 UDPHS Endpoint Control Enable Register UDPHS_EPTCTLENB Write-only –
0x100 + endpoint * 0x20 + 0x08 UDPHS Endpoint Control Disable Register UDPHS_EPTCTLDIS Write-only –
0x100 + endpoint * 0x20 + 0x0C UDPHS Endpoint Control Register UDPHS_EPTCTL Read-only 0x0000_0000
(1)
0x100 + endpoint * 0x20 + 0x10 Reserved (for endpoint) – – –
0x100 + endpoint * 0x20 + 0x14 UDPHS Endpoint Set Status Register UDPHS_EPTSETSTA Write-only –
0x100 + endpoint * 0x20 + 0x18 UDPHS Endpoint Clear Status Register UDPHS_EPTCLRSTA Write-only –
0x100 + endpoint * 0x20 + 0x1C UDPHS Endpoint Status Register UDPHS_EPTSTA Read-only 0x0000_0040
0x120 - 0x1DC UDPHS Endpoint1 to 6
(2)
Registers
0x300 + channel * 0x10 + 0x00 UDPHS DMA Next Descriptor Address Register UDPHS_DMANXTDSC Read-write 0x0000_0000
0x300 + channel * 0x10 + 0x04 UDPHS DMA Channel Address Register UDPHS_DMAADDRESS Read-write 0x0000_0000
0x300 + channel * 0x10 + 0x08 UDPHS DMA Channel Control Register UDPHS_DMACONTROL Read-write 0x0000_0000
0x300 + channel * 0x10 + 0x0C UDPHS DMA Channel Status Register UDPHS_DMASTATUS Read-write 0x0000_0000
0x310 - 0x370 DMA Channel1 to 5
(3)
Registers