Datasheet

522
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
32.6.13 Endpoint Interrupts
Interrupts are enabled in UDPHS_IEN (see Section 32.7.3 ”UDPHS Interrupt Enable Register”) and individually masked
in UDPHS_EPTCTLENBx (see Section 32.7.9 ”UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt
Endpoints)”).
Table 32-5. Endpoint Interrupt Source Masks
SHRT_PCKT Short Packet Interrupt
BUSY_BANK Busy Bank Interrupt
NAK_OUT NAKOUT Interrupt
NAK_IN/ERR_FLUSH NAKIN/Error Flush Interrupt
STALL_SNT/ERR_CRC_NTR
Stall Sent/CRC error/Number of Transaction
Error Interrupt
RX_SETUP/ERR_FL_ISO Received SETUP/Error Flow Interrupt
TXRDY_TRER TX Packet Read/Transaction Error Interrupt
TX_COMPLT Transmitted IN Data Complete Interrupt
RXRDY_TXKL Received OUT Data Interrupt
ERR_OVFLW Overflow Error Interrupt
MDATA_RX MDATA Interrupt
DATAX_RX DATAx Interrupt