Datasheet

492
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
31.7.16 DMAC Channel x [x = 0..7] Control A Register
Name: DMAC_CTRLAx [x = 0..7]
Address: 0xFFFFEC48 (0)[0], 0xFFFFEC70 (0)[1], 0xFFFFEC98 (0)[2], 0xFFFFECC0 (0)[3], 0xFFFFECE8 (0)[4],
0xFFFFED10 (0)[5], 0xFFFFED38 (0)[6], 0xFFFFED60 (0)[7], 0xFFFFEE48 (1)[0], 0xFFFFEE70 (1)[1],
0xFFFFEE98 (1)[2], 0xFFFFEEC0 (1)[3], 0xFFFFEEE8 (1)[4], 0xFFFFEF10 (1)[5], 0xFFFFEF38 (1)[6],
0xFFFFEF60 (1)[7]
Access: Read-write
Reset: 0x00000000
This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” on page 500
• BTSIZE: Buffer Transfer Size
The transfer size relates to the number of transfers to be performed, that is, for writes it refers to the number of source width trans-
fers to perform when DMAC is flow controller. For Reads, BTSIZE refers to the number of transfers completed on the Source
Interface. When this field is set to 0, the DMAC module is automatically disabled when the relevant channel is enabled.
• SCSIZE: Source Chunk Transfer Size
• DCSIZE: Destination Chunk Transfer Size
31 30 29 28 27 26 25 24
DONE – DST_WIDTH – – SRC_WIDTH
23 22 21 20 19 18 17 16
– DCSIZE – SCSIZE
15 14 13 12 11 10 9 8
BTSIZE
76543210
BTSIZE
Value Name Description
000 CHK_1 1 data transferred
001 CHK_4 4 data transferred
010 CHK_8 8 data transferred
011 CHK_16 16 data transferred
Value Name Description
000 CHK_1 1 data transferred
001 CHK_4 4 data transferred
010 CHK_8 8 data transferred
011 CHK_16 16 data transferred