Datasheet

490
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
31.7.14 DMAC Channel x [x = 0..7] Destination Address Register
Name: DMAC_DADDRx [x = 0..7]
Address: 0xFFFFEC40 (0)[0], 0xFFFFEC68 (0)[1], 0xFFFFEC90 (0)[2], 0xFFFFECB8 (0)[3], 0xFFFFECE0 (0)[4],
0xFFFFED08 (0)[5], 0xFFFFED30 (0)[6], 0xFFFFED58 (0)[7], 0xFFFFEE40 (1)[0], 0xFFFFEE68 (1)[1],
0xFFFFEE90 (1)[2], 0xFFFFEEB8 (1)[3], 0xFFFFEEE0 (1)[4], 0xFFFFEF08 (1)[5], 0xFFFFEF30 (1)[6],
0xFFFFEF58 (1)[7]
Access: Read-write
Reset: 0x00000000
This register can only be written if the WPEN bit is cleared in “DMAC Write Protect Mode Register” .
• DADDR: Channel x Destination Address
This register must be aligned with the destination transfer width.
31 30 29 28 27 26 25 24
DADDR
23 22 21 20 19 18 17 16
DADDR
15 14 13 12 11 10 9 8
DADDR
76543210
DADDR