Datasheet

462
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
6. The DMAC transfer proceeds as follows:
1. If the Buffer Transfer Completed Interrupt is unmasked (DMAC_EBCIMR.BTCx = ‘1’, where x is the channel
number), the hardware sets the Buffer Transfer Completed Interrupt when the buffer transfer has completed.
It then stalls until the STALx bit of DMAC_CHSR register is cleared by software, writing ‘1’ to
DMAC_CHER.KEEPx bit, where x is the channel number. If the next buffer is to be the last buffer in the
DMAC transfer, then the buffer complete ISR (interrupt service routine) should clear the automatic mode bit
in the DMAC_CTRLBx.AUTO bit. This puts the DMAC into Row 1 as shown in Table 31-3 on page 455. If
the next buffer is not the last buffer in the DMAC transfer, then the reload bits should remain enabled to keep
the DMAC in Row 4.
2. If the Buffer Transfer Completed Interrupt is masked (DMAC_EBCIMR.BTCx = ‘0’, where x is the channel
number), the hardware does not stall until it detects a write to the Buffer Transfer Completed Interrupt
Enable register DMAC_EBCIER register, but starts the next buffer transfer immediately. In this case, the
software must clear the automatic mode bit in the DMAC_CTRLB to put the DMAC into ROW 1 of Table 31-
3 on page 455 before the last buffer of the DMAC transfer has completed. The transfer is similar to that
shown in Figure 31-9 on page 462. The DMAC transfer flow is shown in Figure 31-10 on page 463.
Figure 31-9. Multi-buffer DMAC Transfer with Source and Destination Address Auto-reloaded
Address of
Source Layer
Address of
Destination Layer
Source Buffers
Destination Buffers
BlockN
Block2
Block1
Block0
SADDR
DADDR