Datasheet

443
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
30.7.10 DDRSDRC High Speed Register
Name: DDRSDRC_HS
Address: 0xFFFFE82C
Access: Read-write
Reset: See Table 30-16
This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 444.
• DIS_ANTICIP_READ: Anticip Read Access
0 = anticip read access is enabled.
1 = anticip read access is disabled (default).
DIS_ANTICIP_READ allows DDR2 read access optimization with multi-port.
As this feature is based on the “bank open policy”, the software must map different buffers in different DDR2 banks to take advan-
tage of that feature.
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
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76543210
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DIS_ANTICIP_RE
AD
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