Datasheet

435
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
30.7.4 DDRSDRC Timing Parameter 0 Register
Name: DDRSDRC_TPR0
Address: 0xFFFFE80C
Access: Read-write
Reset: See Table 30-16
This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 444.
• TRAS: Active to Precharge Delay
Reset Value is 5 cycles.
This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of cycles is
between 0 and 15.
• TRCD: Row to Column Delay
Reset Value is 2 cycles.
This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of cycles is
between 0 and 15.
• TWR: Write Recovery Delay
Reset value is 2 cycles.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 1 and 15.
• TRC: Row Cycle Delay
Reset value is 7 cycles.
This field defines the delay between an Activate command and Refresh command in number of cycles. Number of cycles is
between 0 and 15
• TRP: Row Precharge Delay
Reset Value is 2 cycles.
This field defines the delay between a Precharge Command and another command in number of cycles. Number of cycles is
between 0 and 15.
• TRRD: Active bankA to Active bankB
Reset value is 2 cycles.
This field defines the delay between an Active command in BankA and an active command in bankB in number of cycles. Number
of cycles is between 1 and 15.
31 30 29 28 27 26 25 24
TMRD REDUCE_WRRD TWTR
23 22 21 20 19 18 17 16
TRRD TRP
15 14 13 12 11 10 9 8
TRC TWR
76543210
TRCD TRAS