Datasheet

432
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
30.7.3 DDRSDRC Configuration Register
Name: DDRSDRC_CR
Address: 0xFFFFE808
Access: Read-write
Reset: See Table 30-16
This register can only be written if the bit WPEN is cleared in “DDRSDRC Write Protect Mode Register” on page 444.
• NC: Number of Column Bits
The reset value is 9 column bits.
SDR-SDRAM devices with eight columns in 16-bit mode are not supported.
• NR: Number of Row Bits
The reset value is 12 row bits.
• CAS: CAS Latency
The reset value is 2 cycles.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– DECOD – NB – ACTBST – EBISHARE
15 14 13 12 11 10 9 8
– OCD – – DIS_DLL DIC/DS
76543210
DLL CAS NR NC
NC DDR - Column bits SDR - Column bits
00 98
01 10 9
10 11 10
11 12 11
NR Row bits
00 11
01 12
10 13
11 14
CAS DDR2 CAS Latency SDR CAS Latency
000 Reserved Reserved
001 Reserved Reserved
010 Reserved 2