Datasheet

425

SAM9X35 [DATASHEET]

11055E–ATARM–10-Mar-2014

30.6 Software Interface/SDRAM Organization, Address Mapping

The SDRAM address space is organized into banks, rows and columns. The DDRSDRC maps different memory types

depending on the values set in the DDRSDRC Configuration Register. See Section 30.7.3 “DDRSDRC Configuration

banks addresses for 16-bit memory data bus widths and 32-bit memory data bus widths.

The DDRSDRC supports address mapping in linear mode and interleaved mode.

Linear mode is a method for address mapping where banks alternate at each last SDRAM page of current bank.

Interleaved mode is a method for address mapping where banks alternate at each SDRAM end page of current bank.

The DDRSDRC makes the SDRAM devices access protocol transparent to the user. Table 30-1 to Table 30-15 illustrate

the SDRAM device memory mapping seen by the user in correlation with the device structure. Various configurations are

illustrated.

30.6.1 SDRAM Address Mapping for 16-bit Memory Data Bus Width and Four Banks

Table 30-1. Linear Mapping for SDRAM Configuration, 2K Rows, 512/1024/2048/4096 Columns

CPU Address Line

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bk[1:0] Row[10:0] Column[8:0]

Bk[1:0] Row[10:0] Column[9:0]

Bk[1:0] Row[10:0] Column[10:0]

Bk[1:0] Row[10:0] Column[11:0]

Table 30-2. Linear Mapping for SDRAM Configuration: 4K Rows, 512/1024/2048/4096 Columns

CPU Address Line

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bk[1:0] Row[11:0] Column[8:0]

Bk[1:0] Row[11:0] Column[9:0]

Bk[1:0] Row[11:0] Column[10:0]

Bk[1:0] Row[11:0] Column[11:0]

Table 30-3. Linear Mapping for SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns

CPU Address Line

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bk[1:0] Row[12:0] Column[8:0]

Bk[1:0] Row[12:0] Column[9:0]

Bk[1:0] Row[12:0] Column[10:0]

Bk[1:0] Row[12:0] Column[11:0]