Datasheet

418
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
PASR/DS/TCSR bits are updated before entry into self refresh mode if DDRSDRC does not share an external bus with
another controller or during a refresh command, and a pending read or write access, if DDRSDRC does share an
external bus with another controller. This type of update is a function of the UPD_MR bit (see Section 30.7.7 “DDRSDRC
Low-power Register” on page 439).
The low-power SDR-SDRAM must remain in self refresh mode for a minimum period of TRAS periods and may remain in
self refresh mode for an indefinite period. (See Figure 30-17)
The low-power DDR1-SDRAM must remain in self refresh mode for a minimum of TRFC periods and may remain in self
refresh mode for an indefinite period.
The DDR2-SDRAM must remain in self refresh mode for a minimum of TCKE periods and may remain in self refresh
mode for an indefinite period.
Figure 30-17.Self Refresh Mode Entry, Timeout = 0
Figure 30-18.Self Refresh Mode Entry, Timeout = 1 or 2
NOP READ BST NOP PRCHG NOP ARFSH NOP
0
Trp
Enter Self refresh
Mode
SDCLK
A[12:0]
COMMAND
CKE
BA[1:0]
DQS[0:1]
Da Db
D[15:0]
3
DM[1:0]
NOP READ BST NOP
0
Da Db
64 or 128
wait states
3
PRCHG NOP ARFSH NOP
Trp
Enter Self refresh
Mode
SDCLK
A[12:0]
COMMAND
CKE
BA[1:0]
DQS[1:0]
D[15:0]
DM[1:0]