Datasheet

300
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
26.5 Application Example
26.5.1 Hardware Interface
Table 26-3 details the connections to be applied between the EBI pins and the external devices for each Memory
Controller.
Notes: 1. NWR1 enables upper byte writes. NWR0 enables lower byte writes.
2. NWRx enables corresponding byte x writes. (x = 0,1,2 or 3)
3. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word.
4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word.
5. D24–31 and A20, A23–A25, NCS2, NCS4, NCS5 are multiplexed on PD15–PD31.
Table 26-3. EBI Pins and External Static Device Connections
Signals:
EBI_
Pins of the Interfaced Device
8-bit
Static Device
2 x 8-bit
Static Devices
16-bit
Static Device
4 x 8-bit
Static Devices
2 x 16-bit
Static Devices
32-bit
Static Device
Controller SMC
D0–D7 D0–D7 D0–D7 D0–D7 D0–D7 D0–D7 D0–D7
D8–D15 – D8–D15 D8–D15 D8–D15 D8–15 D8–15
D16–D23 – – – D16–D23 D16–D23 D16–D23
D24–D31
(5))
– – – D24–D31 D24–D31 D24–D31
A0/NBS0 A0 – NLB – NLB
(3)
BE0
A1/NWR2/NBS2/DQM2 A1 A0 A0 WE
(2)
NLB
(4)
BE2
A2–A22
(5)
A[2:22] A[1:21] A[1:21] A[0:20] A[0:20] A[0:20]
A23–A25
(5)
A[23:25] A[22:24] A[22:24] A[21:23] A[21:23] A[21:23]
NCS0 CS CS CS CS CS CS
NCS1/DDRSDCS CS CS CS CS CS CS
NCS2
(5)
CS CS CS CS CS CS
NCS3/NANDCS CS CS CS CS CS CS
NCS4
(5)
CS CS CS CS CS CS
NCS5
(5)
CS CS CS CS CS CS
NRD OEOEOEOEOEOE
NWR0/NWE WE WE
(1)
WE WE
(2)
WE WE
NWR1/NBS1 – WE
(1)
NUB W E
(2)
NUB
(3)
BE1
NWR3/NBS3/DQM3 – – – WE
(2)
NUB
(4)
BE3