Datasheet

291
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
25.7.4 Bus Matrix Priority Registers B For Slaves
Name: MATRIX_PRBS0...MATRIX_PRBS9
Address: 0xFFFFDE84 [0], 0xFFFFDE8C [1], 0xFFFFDE94 [2], 0xFFFFDE9C [3], 0xFFFFDEA4 [4], 0xFFFFDEAC [5],
0xFFFFDEB4 [6], 0xFFFFDEBC [7], 0xFFFFDEC4 [8], 0xFFFFDECC [9]
Access: Read/Write
This register can only be written if the WPEN bit is cleared in the “Write Protection Mode Register” .
• MxPR: Master x Priority
Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
All the masters programmed with the same MxPR value for the slave make up a priority pool.
Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools.
Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2).
See “Arbitration Priority Scheme” on page 284 for details.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––– M10PR
76543210
–– M9PR –– M8PR