Datasheet

219
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
Only PADs PA[20:15], PA[13:11] and PA[4:2] can be configured.
When programming 0x0 in fields, no delay is added (reset value) and the propagation delay of the pad buffers is the
inherent delay of the pad buffer. When programming 0xF in fields, the propagation delay of the corresponding pad is
maximal.
Figure 23-9. Programmable I/O Delays
23.5.13 Programmable I/O Drive
It is possible to configure the I/O drive for pads PA[20:15], PA[13:11] and PA[4:2]. For any details, refer to the product
electrical characteristics.
23.5.14 Programmable Schmitt Trigger
It is possible to configure each input for the Schmitt Trigger. By default the Schmitt trigger is active. Disabling the Schmitt
Trigger is requested when using the QTouch
™
Library.
23.5.15 Write Protection Registers
To prevent any single software error that may corrupt PIO behavior, certain address spaces can be write-protected by
setting the WPEN bit in the “PIO Write Protect Mode Register” (PIO_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the PIO Write Protect Status Register
(PIO_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the PIO Write Protect Mode Register (PIO_WPMR) with the appropriate access key,
WPKEY.
The protected registers are:
 “PIO Enable Register” on page 225
 “PIO Disable Register” on page 225
 “PIO Output Enable Register” on page 226
 “PIO Output Disable Register” on page 227
 “PIO Input Filter Enable Register” on page 228
 “PIO Input Filter Disable Register” on page 228
 “PIO Multi-driver Enable Register” on page 233
 “PIO Multi-driver Disable Register” on page 234
 “PIO Pull Up Disable Register” on page 235
DELAY1
Programmable Delay Line
PIO
PAout[0]
PAin[0]
DELAY2
Programmable Delay Line
DELAYx
Programmable Delay Line
PAout[1]
PAin[1]
PAout[2]
PAin[2]