Datasheet

182
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
Depending on the system used, 19 peripheral clocks can be enabled or disabled. The PMC_PCR provides a clear
view as to which peripheral clock is enabled.
Note: Each enabled peripheral clock corresponds to Master Clock.
Code Examples:
write_register(PMC_PCER,0x00000110)
Peripheral clocks 4 and 8 are enabled.
write_register(PMC_PCDR,0x00000010)
Peripheral clock 4 is disabled.
22.12 Clock Switching Details
22.12.1 Master Clock Switching Timings
Table 22-1 and Table 22-2 give the worst case timings required for the Master Clock to switch from one selected clock to
another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of
64 clock cycles of the new selected clock has to be added.
Notes: 1. PLL designates either the PLLA or the UPLL Clock.
2. PLLCOUNT designates either PLLACOUNT or UPLLCOUNT.
Table 22-1. Clock Switching Timings (Worst Case)
Fro
m Main Clock SLCK PLL Clock
To
Main
Clock
–
4 x SLCK +
2.5 x Main Clock
3 x PLL Clock +
4 x SLCK +
1 x Main Clock
SLCK
0.5 x Main Clock +
4.5 x SLCK
–
3 x PLL Clock +
5 x SLCK
PLL Clock
0.5 x Main Clock +
4 x SLCK +
PLLCOUNT x SLCK +
2.5 x PLLx Clock
2.5 x PLL Clock +
5 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
4 x SLCK +
PLLCOUNT x SLCK
Table 22-2. Clock Switching Timings between Two PLLs (Worst Case)
Fro
m PLLA Clock UPLL Clock
To
PLLA Clock
2.5 x PLLA Clock +
4 x SLCK +
PLLACOUNT x SLCK
3 x PLLA Clock +
4 x SLCK +
1.5 x PLLA Clock
UPLL
Clock
3 x UPLL Clock +
4 x SLCK +
1.5 x UPLL Clock
2.5 x UPLL Clock +
4 x SLCK +
UPLLCOUNT x SLCK