Datasheet

162
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
20.3 Block Diagram
Figure 20-1. Block Diagram
RCEN, OSC32EN, OSCSEL and OSC32BYP bits are located in the Slow Clock Configuration Register (SCKC_CR)
located at the address 0xFFFFFE50 in the backed up part of the System Controller and, thus, they are preserved while
VDDBU is present.
After a VDDBU power on reset, the default configuration is RCEN = 1, OSC32EN = 0 and OSCSEL = 0, allowing the
system to start on the internal 32 kHz RC oscillator.
The programmer controls the slow clock switching by software and so must take precautions during the switching phase.
On Chip
RC OSC
Slow Clock
SLCK
XIN32
XOUT32
Slow Clock
Oscillator
OSC32EN
RCEN
OSCSEL
OSC32BYP