Datasheet

1287
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
SPI:
Replaced references to “Advanced Interrupt Controller” with “Interrupt Controller”.
Section 35.8.9 “SPI Chip Select Register”, added a phrase specifying when this register can be written and
updated the table in “BITS: Bits Per Transfer” : reserved bits are from 9 to 15.
Section 35.7.3.5 “Peripheral Selection”, corrected a cross-reference for the footnote.
Section 35.8.10 “SPI Write Protection Mode Register”, replaced “SPIWPKEY” with “WPKEY” and “SPIWPEN”
with “WPEN” and added a list of write-protected registers.
Section 35.8.11 “SPI Write Protection Status Register”, replaced “SPIWPVSRC” with “WPVSRC” and
“SPIWPVS” with “WPVS” and updated the description of “WPVS: Write Protection Violation Status” .
Section 35.2 “Embedded Characteristics”, removed redundant text line and updated the line “Programmable
Transfer Delay Between Consecutive ...”.
Section 35.8.1 “SPI Control Register”, removed the last phrase in “SWRST: SPI Software Reset” .
7513
7931
8025
8136
8210
8362
TC:
The number of identical 32-bit Timer Counter channels is not three anymore but six.
Section 36.2 “Embedded Characteristics”, updated the line on input/output signals.
Section 36.7 “Timer Counter (TC) User Interface”, added a row for reserved registers (offsets ‘0xC8 - 0xD4’) in
Table 36-5 “Register Mapping”.
Updated the order of register description sections to match the order in Table 36-5 “Register Mapping”.
8648
rfo
PWM:
Section 37.5.2 “Power Management”, updated the second paragraph.
Section 37.2 “Embedded characteristics”, updated the last line of the list.
8105
rfo
TWI:
Section 38.1 “Description”, fixed a typo: removed “20” at the end of the 1st paragraph.
Added three paragraphs in Section 38.8.5 “Master Receiver Mode”.
Added Table 38-11 “Master Read Clock Stretching with Multiple Data Bytes”.
Added Section 38.11 “Write Protection System”.
Added Section 38.8.7.1 “Data Transmit with the DMA” and Section 38.8.7.2 “Data Receive with the DMA”.
Updated Section 38.12 “Two-wire Interface (TWI) User Interface”:
- Table 38-6 “Register Mapping”
, added rows for Protection Mode Register (0xE4) and Protection Status Register
- added Section 38.12.12 “TWI Write Protection Mode Register” and Section 38.12.13 “TWI Write Protection
Status Register”
- added a phrase specifying when the TWI_SMR and TWI_CWGR registers can be written in Section 38.12.3
“TWI Slave Mode Register” and Section 38.12.5 “TWI Clock Waveform Generator Register”.
7921
8426
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11055C Comments
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