Datasheet

1284
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
GPBR:
Section 19.3.1 “General Purpose Backup Register x”, removed ‘x’ from the bitfield names in the SYS_GPBRx
register table and in the description below.
7990
SCKC:
Section 20.3 “Block Diagram”, updated the first paragraph: the RCEN, OSC32EN, OSCSEL and OSC32BYP bits
are located not in Slow Clock Control Register (SCKCR) but in Slow Clock Configuration Register (SCKC_CR).
Fixed Figure 20-1 “Block Diagram” for better representation.
8322
rfo
CKGR:
Section 21.6.2 “Switch from Internal 12 MHz RC Oscillator to the 12 MHz Crystal”, fixed a typo in the sequence
order: MAINRDY --> MOSCXTS
.
Section 21.7 “Divider and PLLA Block”, added the PLLADIV2 block between the PLLA block and the PLLACK
reference in Figure 21-6 “Divider and PLLA Block Diagram”.
Updated Crystal Oscillator range from “3 to 20 MHz” to “12 to 16 MHz” in Section 21.2 “Embedded
Characteristics”, Section 21.5 “Main Clock”, Figure 21-3 “Main Clock Block Diagram”, Section 21.6.6 “12 to 16
MHz Crystal Oscillator”, Section 21.6.7 “Main Clock Oscillator Selection”, and Section 21.6.8 “Main Clock
Frequency Counter”.
Section 21.3 “CKGR Block Diagram”, updated the UPLL block connections in Figure 21-1 “Clock Generator
Block Diagram”.
8327
8401
8413
PMC:
Section 22.4 “Block Diagram”, removed the “/1, /2” divider block in Figure 22-2 “General Clock Block Diagram”.
Section 22.13 “Power Management Controller (PMC) User Interface”, updated the CKGR_MOR reset value
(0x0100_0008 --> 0x0000_0008) in Table 22-3 “Register Mapping”.
8401
8447
PIO:
Section 23.4.4 “Interrupt Generation”, updated the 1st paragraph.
Section 23.5.10 “Input Edge/Level Interrupt”, replaced “...to the Advanced Interrupt Controller (AIC)” with “...to
the interrupt controller” in the paragraph “When an input Edge or Level is detected...”.
8324
EBI:
Section 26.5.1 “Hardware Interface”, fixed typos in Table 26-4 “EBI Pins and External Device Connections”:
the power supply of A20, A23, A24, A25, NCS2, NCS4 and NCS5 is VDDNF and not VDDIOM.
Updated EBIx pin data in Table 26-2 “EBI Pins and Memory Controllers I/O Lines Connections” and added A13
as SDRAMC pin in the A15 line in Table 26-4 “EBI Pins and External Device Connections”.
8179
rfo
PMECC:
Figure 27-2 “Software/Hardware Multibit Error Correction Dataflow”, “READ PAGE” and “PROGRAM PAGE”
positions swapped in the flow chart.
Figure 27-5 “Read Operation with Spare Decoding”, configuration revised as ”...SPAREEN set to One and AUTO
set to Zero.”
Section 27.2 “Embedded Characteristics”, added a line about supporting 8-bit Nand Flash data bus.
Section 27.6.11 “PMECC Interrupt Status Register”, replaced duplicate bits 31 - 24 with missing 7 - 0 in the
PMECC_ISR register table.
7495
8403
rfo
PMERRLOC:
Section 28.5.10 “Error Location SIGMAx Register”, “SIGMAN” bitfield name replaced with “SIGMAx” in the
PMERRLOC_SIGMAx [x=0..24] register table.
8339
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