Datasheet

1270
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
Figure 47-28.USART SPI Slave mode: (Mode 0 or 3)
SCK
MISO
MOSI
SPI
9
SPI
10
SPI
11
NSS
SPI
14
SPI
15
Table 47-46. USART SPI Timings
Symbol Parameter Conditions Min Max Unit
Master Mode
SPI
0
SCK Period
1.8V domain
(1)
3.3V domain
(2)
MCK/6 ns
SPI
1
Input Data Setup Time
1.8V domain
(1)
3.3V domain
(2)
0.5 × MCK + 4.1
0.5 × MCK + 3.8
ns
SPI
2
Input Data Hold Time
1.8V domain
(1)
3.3V domain
(2)
1.5 × MCK + 0.9
1.5 × MCK + 1.1
ns
SPI
3
Chip Select Active to Serial Clock
1.8V domain
(1)
3.3V domain
(2)
1.5 × SCK - 2.0
1.5 × SCK - 2.6
ns
SPI
4
Output Data Setup Time
1.8V domain
(1)
3.3V domain
(2)
0
0
7.6
8.0
ns
SPI
5
Serial Clock to Chip Select Inactive
1.8V domain
(1)
3.3V domain
(2)
1 × SCK - 6.7
1 × SCK - 7.5
ns
Slave Mode
SPI
6
SCK falling to MISO
1.8V domain
(1)
3.3V domain
(2)
3.7
2.9
19.9
16.9
ns
SPI
7
MOSI Setup time before SCK rises
1.8V domain
(1)
3.3V domain
(2)
2 × MCK + 3.4
2 × MCK + 3.1
ns
SPI
8
MOSI Hold time after SCK rises
1.8V domain
(1)
3.3V domain
(2)
1.6
1.4
ns
SPI
9
SCK rising to MISO
1.8V domain
(1)
3.3V domain
(2)
3.4
2.7
19.4
16.5
ns