Datasheet

1177
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
46.7.56 High End Overlay Layer Interrupt Disable Register
Name: LCDC_HEOIDR
Address: 0xF8038290
Access: Write-only
Reset: 0x00000000
• DMA: End of DMA Transfer Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• DSCR: Descriptor Loaded Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• ADD: Head Descriptor Loaded Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• DONE: End of List Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• OVR: Overflow Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• UDMA: End of DMA Transfer for U or UV Chrominance Component Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• UDSCR: Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
• UADD: Head Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register
0: No effect.
1: Interrupt source is disabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– VOVR VDONE VADD VDSCR VDMA – –
15 14 13 12 11 10 9 8
– UOVR UDONE UADD UDSCR UDMA – –
76543210
– OVR DONE ADD DSCR DMA – –