Datasheet

1117
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
0x000002D8 High End Overlay Configuration Register 3 LCDC_HEOCFG3 Read-write 0x00000000
0x000002DC High End Overlay Configuration Register 4 LCDC_HEOCFG4 Read-write 0x00000000
0x000002E0 High End Overlay Configuration Register 5 LCDC_HEOCFG5 Read-write 0x00000000
0x000002E4 High End Overlay Configuration Register 6 LCDC_HEOCFG6 Read-write 0x00000000
0x000002E8 High End Overlay Configuration Register 7 LCDC_HEOCFG7 Read-write 0x00000000
0x000002EC High End Overlay Configuration Register 8 LCDC_HEOCFG8 Read-write 0x00000000
0x000002F0 High End Overlay Configuration Register 9 LCDC_HEOCFG9 Read-write 0x00000000
0x000002F4 High End Overlay Configuration Register 10 LCDC_HEOCFG10 Read-write 0x00000000
0x000002F8 High End Overlay Configuration Register 11 LCDC_HEOCFG11 Read-write 0x00000000
0x000002FC High End Overlay Configuration Register 12 LCDC_HEOCFG12 Read-write 0x00000000
0x00000300 High End Overlay Configuration Register 13 LCDC_HEOCFG13 Read-write 0x00000000
0x00000304 High End Overlay Configuration Register 14 LCDC_HEOCFG14 Read-write 0x00000000
0x00000308 High End Overlay Configuration Register 15 LCDC_HEOCFG15 Read-write 0x00000000
0x0000030C High End Overlay Configuration Register 16 LCDC_HEOCFG16 Read-write 0x00000000
0x310-0x33C Reserved – – –
0x00000340 Hardware Cursor Channel Enable Register LCDC_HCRCHER Write-only 0x00000000
0x00000344 Hardware Cursor Channel Disable Register LCDC_HCRCHDR Write-only 0x00000000
0x00000348 Hardware Cursor Channel Status Register LCDC_HCRCHSR Read-only 0x00000000
0x0000034C Hardware Cursor Interrupt Enable Register LCDC_HCRIER Write-only 0x00000000
0x00000350 Hardware Cursor Interrupt Disable Register LCDC_HCRIDR Write-only 0x00000000
0x00000354 Hardware Cursor Interrupt Mask Register LCDC_HCRIMR Read-only 0x00000000
0x00000358 Hardware Cursor Interrupt Status Register LCDC_HCRISR Read-only 0x00000000
0x0000035C Hardware Cursor DMA Head Register LCDC_HCRHEAD Read-write 0x00000000
0x00000360 Hardware cursor DMA Address Register LCDC_HCRADDR Read-write 0x00000000
0x00000364 Hardware Cursor DMA Control Register LCDC_HCRCTRL Read-write 0x00000000
0x00000368 Hardware Cursor DMA NExt Register LCDC_HCRNEXT Read-write 0x00000000
0x0000036C Hardware Cursor Configuration 0 Register LCDC_HCRCFG0 Read-write 0x00000000
0x00000370 Hardware Cursor Configuration 1 Register LCDC_HCRCFG1 Read-write 0x00000000
0x00000374 Hardware Cursor Configuration 2 Register LCDC_HCRCFG2 Read-write 0x00000000
0x00000378 Hardware Cursor Configuration 3 Register LCDC_HCRCFG3 Read-write 0x00000000
0x0000037C Hardware Cursor Configuration 4 Register LCDC_HCRCFG4 Read-write 0x00000000
0x00000380 Reserved – – –
0x00000384 Hardware Cursor Configuration 6 Register LCDC_HCRCFG6 Read-write 0x00000000
0x00000388 Hardware Cursor Configuration 7 Register LCDC_HCRCFG7 Read-write 0x00000000
0x0000038C Hardware Cursor Configuration 8 Register LCDC_HCRCFG8 Read-write 0x00000000
0x00000390 Hardware Cursor Configuration 9 Register LCDC_HCRCFG9 Read-write 0x00000000
0x394-0x3FC Reserved – – –
0x400 Base CLUT Register 0
(1)
LCDC_BASECLUT0 Read-write 0x00000000
... ... ... ... ...
Table 46-55. Register Mapping (Continued)
Offset Register Name Access Reset