Datasheet

968
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
42.7.5 ADC Channel Enable Register
Name: ADC_CHER
Address: 0xF804C010
Access: Write-only
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 981.
• CHx: Channel x Enable
0 = No effect.
1 = Enables the corresponding channel.
Note: If USEQ = 1 in ADC_MR register, CHx corresponds to the xth channel of the sequence described in ADC_SEQR1 and
ADC_SEQR2.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––CH11CH10CH9CH8
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0