Datasheet

961
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
42.6.10 Write Protected Registers
To prevent any single software error that may corrupt ADC behavior, certain address spaces can be write-protected by
setting the WPEN bit in the “ADC Write Protect Mode Register” (ADC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the ADC Write Protect Status Register
(ADC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset by reading the ADC Write Protect Status Register (ADC_WPSR).
The protected registers are:
 “ADC Mode Register” on page 964
 “ADC Channel Sequence 1 Register” on page 966
 “ADC Channel Sequence 2 Register” on page 967
 “ADC Channel Enable Register” on page 968
 “ADC Channel Disable Register” on page 969
 “ADC Extended Mode Register” on page 977
 “ADC Compare Window Register” on page 978
 “ADC Trigger Register” on page 980